![]() ![]() Active-HDL is an HDL-based FPGA Design and Simulation solution that supports the newest FPGA devices available from all leading FPGA vendors. Popular with designers for more than 15 years for FPGA design entry and simulation due to its award-winning and intuitive GUI and high performance simulator, Active-HDL now offers support for 64-bit simulation to meet the growing demand of simulation of larger designs. 1 (64bit) 478.7 mb Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL 10.1.
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